Accelerator Reliability Workshop 2026 (ARW2026)

LANSCE FPGA Based Chopper Pattern Fault Chassis

Not scheduled

1h

Hotel Aomori

Poster Poster session

Speaker

Joseph Snyder (Los Alamos National Laboratory)

Description

The H- species of beam at the LANSCE accelerator is chopped into
one of three patterns - Micro Pulse Enable Gate (MPEG), Long
Bunch Enable Gate (LBEG), and H-GX. Both variations have variable
chopping patterns with a minimum micropulse length of 20ns and a
nominal period of 360ns. Accurate comparison of the prescribed
chopping pattern Vs. the actual chopped beam has never been
possible with the legacy hardware. Furthermore, the existing
Emitter Coupled Logic (ECL) system was outdated, and replacement
components were no longer available. By using differential
Positive ECL logic gates and 1GHz counters, the signals can be
observed directly in hardware with 1ns of resolution. A Field
Programmable Gate Array (FPGA) is used to analyze the collected
data and process faults accordingly. Fault information is passed
to the LANSCE Fast Protect System, which terminates production of
beam for the remainder of the 120Hz machine cycle.